TITLE
MODELING AND SIMULATION OF A SINGLE-CYCLE MIPS MICROARCHITECTURE AS AN EDUCATIONAL TOOL FOR COMPUTER ARCHITECTURE
AUTHOR(S)
Petar Minev*, Ilian Varbov, Valentina Kukenska, Matyo Dinev
ABSTRACT
This report details the design, modeling, and simulation of a Single-Cycle MIPS Microarchitecture using the VHDL hardware description language. The primary objective of this project is to create a robust and pedagogically effective model suitable for use as an educational tool in introductory Computer Architecture and Organization courses. The work focuses on implementing a Reduced Instruction Set Computing (RISC) approach, specifically covering a critical subset of the MIPS Instruction Set Architecture (ISA), including R-type, I-type, and basic control flow instructions. The single-cycle design was chosen for its straightforward pipeline-less operation, which facilitates the clear understanding and visualization of the core execution phases: Instruction Fetch, Decode, Execute, Memory Access, and Write Back. The document provides an in-depth analysis of the main functional blocks—the Program Counter (PC), the
Register File, the Arithmetic Logic Unit (ALU), and the Control Unit—and demonstrates their seamless integration within the Datapath. The VHDL implementation is verified through extensive testbenches, generating precise timing diagrams that confirm functional correctness and serve as illustrative examples for students. The resulting
model successfully bridges the gap between theoretical knowledge and practical hardware implementation, making complex processor concepts accessible to learners.
DOI
How to cite this article:
Petar Minev*, Ilian Varbov, Valentina Kukenska, Matyo Dinev, MODELING AND SIMULATION OF A SINGLE-CYCLE MIPS MICROARCHITECTURE AS AN EDUCATIONAL TOOL FOR COMPUTER ARCHITECTURE, UNITECH – SELECTED PAPERS - 2025